In software development, make is a utility that automatically builds executable programs and libraries from source code by reading files called Makefiles which specify how to derive the target program. Make can decide where to start through topological sorting. Though Integrated Development Environments and language-specific compiler features can also be used to manage the build process in modern systems, make remains widely used, especially in Unix-based platforms.

Though its primary use is as described above, make is not restricted to just creating executable programs from source files. Any process that involves transforming a dependency file to a target result (by executing some number of arbitrary commands) is applicable to make. To cite an example, make could be used to detect a change made to an image file (the dependency) and the target actions that result might be to convert the file to some specific format, copy the result into a content management system, and then send e-mail to a predefined set of users that the above actions were performed.


  • make is used to help compile large software packages.
  • It uses a configuration file named Makefile or makefile to define dependency relationships among files.
  • One example of a dependency is a C source file util.c which uses the #include directive to include config.h. Any time you change config.h, you need to recompile util.c.
  • The basic idea behind make is to define targets, list their dependencies, and what step(s) are needed to build the targets.
  • make knows about some "natural" dependencies on its own, for example that output file util.o depends on source file util.c.
  • make also knows about some "natural" ways to build targets on its own, for example running cc -c to build an object file from a C source code file.
  • make uses the dependencies you describe in Makefile along with the time the files were last modified to decide what file(s) need to be operated upon, and how to operate on them.
  • The general form of a Makefile entry is:

    	target1 target2 ... : depend1 depend2

  • You can specify more than one target, but that is rare. Usually you just define one target.
  • Often you list more than one dependency.
  • operation(s) lists shell commands necessary to build the listed targets.
  • Be sure to use tabs to indent all operations. Some versions of make are very picky about that. emacs may substitute spaces for tabs.
  • Example: executable file foo gets built from two C source files foo.c and bar.c, the Makefile could be:

    	foo: foo.o bar.o
    		cc -O foo.o bar.o -o foo
    	foo.o: foo.c
    		cc -c foo.c
    	bar.o: bar.c
    		cc -c bar.c

  • That example doesn't take advantage of any of make's internal knowledge though, the lines saying how to generate the object files from the C source files are not needed.
  • This simple example doesn't show much of how make becomes invaluable for larger projects.
  • Now suppose bar.c includes config.h to obtain some of its data structures.
  • The example now becomes:

    	foo: foo.o bar.o
    		cc -O foo.o bar.o -o foo
    	bar.o: config.h

  • Now whenever you edit config.h, make will recompile bar.c for you.
  • As the number of source and include files increases, make becomes more and more valuable.
  • macros can be used in Makefile to make updating it a bit easier.
  • Typical use of the macros is to list all object files for a target, for example:

    	OBJ=foo.o bar.o
    	foo: $(OBJ)
    		cc -O $(OBJ) -o foo

  • Macros are also often used for listing the programming libraries needed for the final linking, the C compiler options, etc.
  • make has several macros that it keeps on its own, which you can override if you want to.
  • The CC macro defines the C compiler that make will use. By default it is cc, but if you want to use gcc instead of cc, explicitly set the CC macro.
  • You may override the default CC macro in Makefile:


  • You may also override it on the command line:

    	% make "CC=gcc"

  • The same will work if you want to use g++.
  • changing the CFLAGS macro sets what flags the compiler gets called with.
  • See the manual page (man make) for the complete list of internal macros.
  • With no command line arguments, make will build the first target in Makefile.
  • Can give a target on the command line to have make build that instead.
  • clean is a target often provided to remove object files, executables, and any other things the building process may leave behind.
  • install is a target often provided to handle copying the executable(s) to where they should be installed, set permissions properly, install any library files or configuration files, etc.
  • The -n command line switch to make will show you what make would do of you were to run it but doesn't actually do it.